详细说明:这是一个IIC的接口程序,是夏宇闻编的书《verilog 数字系统设计教程》的IIC的源码,很通俗易懂-IIC interface procedures, Xia Wen is the book series "verilog Digital System Design Guide," the IIC the source, very user-friendly
[vgatest.rar] - VGA实验的verilog HDL代码用于FPGA
[uart_v11.zip] - uart串口的vhdl语言程序。本人调试过 ,非常好用
[I2C.rar] - NIOSII I2C源程序,是sopc嵌入式软核的!
[inpoly.zip] - 判断点是否在多边形之内
[I2C_slave_model.rar] - 完整的I2C slave model以及spec詳附在內,適合想利用verilog開發此類傳輸的人參考
[DS1631Control.rar] - 一个完整的通过iic总线控制Dallas公司的温度传感芯片DS1631采集温度数据的verilog代码
[key.rar] - 使用verilog实现的4x4的键盘,但是把延时程序去掉了,可以给大家参考
[verilog_Development_Board_Sources.rar] - 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马
[I2CSlave.rar] - verilog HDL实现的I2C Slave模拟
[北航夏宇闻verilog讲稿ppt.rar] - 北航夏宇闻verilog讲稿ppt
[vhdl_i2c.zip] - 7. iic 接口EEPROM 存取实验 按动开发板键盘某个键CPLD 将拨码开关的数据写入EEPROM 的某个地址,按动另 外一个键,将刚写入的数据读回CPLD,并在数码管上显示。帮助读者掌握I2C 的总线协 议和EEPROM 的读写方法。
[uart_v11.zip] - uart串口的vhdl语言程序。本人调试过 ,非常好用
[I2C.rar] - NIOSII I2C源程序,是sopc嵌入式软核的!
[inpoly.zip] - 判断点是否在多边形之内
[I2C_slave_model.rar] - 完整的I2C slave model以及spec詳附在內,適合想利用verilog開發此類傳輸的人參考
[DS1631Control.rar] - 一个完整的通过iic总线控制Dallas公司的温度传感芯片DS1631采集温度数据的verilog代码
[key.rar] - 使用verilog实现的4x4的键盘,但是把延时程序去掉了,可以给大家参考
[verilog_Development_Board_Sources.rar] - 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马
[I2CSlave.rar] - verilog HDL实现的I2C Slave模拟
[北航夏宇闻verilog讲稿ppt.rar] - 北航夏宇闻verilog讲稿ppt
[vhdl_i2c.zip] - 7. iic 接口EEPROM 存取实验 按动开发板键盘某个键CPLD 将拨码开关的数据写入EEPROM 的某个地址,按动另 外一个键,将刚写入的数据读回CPLD,并在数码管上显示。帮助读者掌握I2C 的总线协 议和EEPROM 的读写方法。
文件列表(点击判断是否您需要的文件):
i2c
...\bench
...\.....\CVS
...\.....\verilog
...\.....\.......\CVS
...\.....\.......\...\Entries
...\.....\.......\i2c_slave_model.v
...\.....\.......\i2c_slave_model.v.bak
...\.....\.......\spi_slave_model.v
...\.....\.......\spi_slave_model.v.bak
...\.....\.......\tst_bench_top.v
...\.....\.......\tst_bench_top.v.bak
...\.....\.......\wb_master_model.v
...\.....\.......\wb_master_model.v.bak
...\CVS
...\doc
...\...\CVS
...\...\i2c_specs.pdf
...\...\src
...\...\...\CVS
...\...\...\I2C_specs.doc
...\rtl
...\...\CVS
...\...\verilog
...\...\.......\CVS
...\...\.......\...\Entries
...\...\.......\i2c_master_bit_ctrl.v
...\...\.......\i2c_master_bit_ctrl.v.bak
...\...\.......\i2c_master_byte_ctrl.v
...\...\.......\i2c_master_byte_ctrl.v.bak
...\...\.......\i2c_master_defines.v
...\...\.......\i2c_master_top.v
...\...\.......\i2c_master_top.v.bak
...\...\vhdl
...\...\....\CVS
...\...\....\...\Entries
...\...\....\I2C.VHD
...\...\....\i2c_master_bit_ctrl.vhd
...\...\....\i2c_master_byte_ctrl.vhd
...\...\....\i2c_master_top.vhd
...\...\....\readme
...\...\....\tst_ds1621.vhd
...\sim
...\...\CVS
...\...\i2c.cr.mti
...\...\i2c.mpf
...\...\i2c_verilog
...\...\...........\CVS
...\...\...........\run
...\...\...........\...\bench.vcd
...\...\...........\...\CVS
...\...\...........\...\INCA_libs
...\...\...........\...\.........\CVS
...\...\...........\...\ncverilog.log
...\...\...........\...\run
...\...\...........\...\waves
...\...\...........\...\.....\CVS
... ...
i2c
...\bench
...\.....\CVS
...\.....\verilog
...\.....\.......\CVS
...\.....\.......\...\Entries
...\.....\.......\i2c_slave_model.v
...\.....\.......\i2c_slave_model.v.bak
...\.....\.......\spi_slave_model.v
...\.....\.......\spi_slave_model.v.bak
...\.....\.......\tst_bench_top.v
...\.....\.......\tst_bench_top.v.bak
...\.....\.......\wb_master_model.v
...\.....\.......\wb_master_model.v.bak
...\CVS
...\doc
...\...\CVS
...\...\i2c_specs.pdf
...\...\src
...\...\...\CVS
...\...\...\I2C_specs.doc
...\rtl
...\...\CVS
...\...\verilog
...\...\.......\CVS
...\...\.......\...\Entries
...\...\.......\i2c_master_bit_ctrl.v
...\...\.......\i2c_master_bit_ctrl.v.bak
...\...\.......\i2c_master_byte_ctrl.v
...\...\.......\i2c_master_byte_ctrl.v.bak
...\...\.......\i2c_master_defines.v
...\...\.......\i2c_master_top.v
...\...\.......\i2c_master_top.v.bak
...\...\vhdl
...\...\....\CVS
...\...\....\...\Entries
...\...\....\I2C.VHD
...\...\....\i2c_master_bit_ctrl.vhd
...\...\....\i2c_master_byte_ctrl.vhd
...\...\....\i2c_master_top.vhd
...\...\....\readme
...\...\....\tst_ds1621.vhd
...\sim
...\...\CVS
...\...\i2c.cr.mti
...\...\i2c.mpf
...\...\i2c_verilog
...\...\...........\CVS
...\...\...........\run
...\...\...........\...\bench.vcd
...\...\...........\...\CVS
...\...\...........\...\INCA_libs
...\...\...........\...\.........\CVS
...\...\...........\...\ncverilog.log
...\...\...........\...\run
...\...\...........\...\waves
...\...\...........\...\.....\CVS
... ...