详细说明:AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档,和此代码的测试程序,可作为一个IP核直接使用,可减少开发人员的设计时间。-AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use, developers can reduce design time.
相关搜索:
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[rijndael(全).zip] - rijndael(全).zip,已经通过aes认证。这个源码包是全的,含有std_defs2.h文件。这儿有很多rain doll源码包都不全
[aes.rar] - 基于fpga的aes高速实现,介绍了算法实现的过程,仿真结果。
[正确的aes.rar] - 这是一个正确的用C语言写的aes程序可以直接用结果是正确的.加密速度比较快吧.
[pci_core.rar] - PCI logicore,在某网站上下载的ip核文件,希望具有参考价值,
[加密机与解密机实例源码.rar] - 加密解密的代码,从网络上找到,应该对写共享软件有用。
[has160.ZIP] - has160哈希函数。用散列的方法将明文处理达到加密的效果。
[Advanced_E2022991032006(1).zip] - aes加密算法实现 AES加密算法实现 Aes加密算法实现
[aes.rar] - 基于fpga的aes高速实现,介绍了算法实现的过程,仿真结果。
[正确的aes.rar] - 这是一个正确的用C语言写的aes程序可以直接用结果是正确的.加密速度比较快吧.
[pci_core.rar] - PCI logicore,在某网站上下载的ip核文件,希望具有参考价值,
[加密机与解密机实例源码.rar] - 加密解密的代码,从网络上找到,应该对写共享软件有用。
[has160.ZIP] - has160哈希函数。用散列的方法将明文处理达到加密的效果。
[Advanced_E2022991032006(1).zip] - aes加密算法实现 AES加密算法实现 Aes加密算法实现
文件列表(点击判断是否您需要的文件):
aes_core
........\bench
........\.....\CVS
........\.....\verilog
........\.....\.......\CVS
........\.....\.......\test_bench_top.v
........\CVS
........\doc
........\...\aes.pdf
........\...\CVS
........\rtl
........\...\CVS
........\...\verilog
........\...\.......\aes_cipher_top.v
........\...\.......\aes_inv_cipher_top.v
........\...\.......\aes_inv_sbox.v
........\...\.......\aes_key_expand_128.v
........\...\.......\aes_rcon.v
........\...\.......\aes_sbox.v
........\...\.......\CVS
........\...\.......\...\Entries
........\sim
........\...\CVS
........\...\rtl_sim
........\...\.......\bin
........\...\.......\...\CVS
........\...\.......\...\Makefile
........\...\.......\CVS
........\...\.......\run
........\...\.......\...\CVS
........\...\.......\...\waves
........\...\.......\...\.....\CVS
........\...\.......\...\.....\waves.do
........\syn
........\...\bin
........\...\...\comp.dc
........\...\...\CVS
........\...\...\design_spec.dc
........\...\...\lib_spec.dc
........\...\...\read.dc
........\...\CVS
........\vim_session.vim
aes_core
........\bench
........\.....\CVS
........\.....\verilog
........\.....\.......\CVS
........\.....\.......\test_bench_top.v
........\CVS
........\doc
........\...\aes.pdf
........\...\CVS
........\rtl
........\...\CVS
........\...\verilog
........\...\.......\aes_cipher_top.v
........\...\.......\aes_inv_cipher_top.v
........\...\.......\aes_inv_sbox.v
........\...\.......\aes_key_expand_128.v
........\...\.......\aes_rcon.v
........\...\.......\aes_sbox.v
........\...\.......\CVS
........\...\.......\...\Entries
........\sim
........\...\CVS
........\...\rtl_sim
........\...\.......\bin
........\...\.......\...\CVS
........\...\.......\...\Makefile
........\...\.......\CVS
........\...\.......\run
........\...\.......\...\CVS
........\...\.......\...\waves
........\...\.......\...\.....\CVS
........\...\.......\...\.....\waves.do
........\syn
........\...\bin
........\...\...\comp.dc
........\...\...\CVS
........\...\...\design_spec.dc
........\...\...\lib_spec.dc
........\...\...\read.dc
........\...\CVS
........\vim_session.vim